What this article answers
Article summary
To choose between a seal-in circuit and a latch instruction in PLC logic, evaluate power-loss recovery first. Seal-in circuits lose state when power or rung continuity is removed, which helps prevent unexpected restart. Latch instructions retain state until explicitly cleared, so they require deliberate reset strategy and validation.
A common misconception is that seal-in and latch logic are interchangeable because both can keep an output on. They are not interchangeable where restart behavior matters. The real distinction is memory retention under scan interruption, power loss, and reboot.
Ampergon Vallis Metric: In an internal review of 500 user-built motor-control programs created in OLLA Lab simulation exercises, 68% of programs using retentive latch patterns did not include a complete first-scan reset or equivalent restart-clear routine. Methodology: Sample size = 500 user-generated motor-control exercises; task definition = review of retentive output/state handling during simulated power-cycle tests; baseline comparator = presence or absence of explicit restart-clear logic; time window = Jan 1, 2026 to Mar 15, 2026. This supports one narrow point: restart handling is often under-specified in junior logic. It does not support any broader claim about industry-wide programming quality.
What is the fundamental difference between seal-in and latch logic?
The fundamental difference is state retention.
A seal-in circuit holds an output on by feeding back a non-retentive confirmation path through the rung, typically using a standard output instruction such as OTE and a parallel branch around the start condition. If the rung goes false, controller memory clears that output on the next scan. If power is lost, the output does not remember that prior true state unless separate retentive handling has been added elsewhere.
A latch instruction such as OTL/OTU or platform-specific SET/RESET stores a bit until an explicit unlatch or reset instruction clears it. That stored state can survive scan interruptions and, depending on controller memory configuration and platform behavior, may survive power cycles as a retentive state.
That is the whole argument in one line: seal-in logic depends on present conditions; latch logic depends on stored history.
Seal-In vs. Latch Execution Matrix
| Attribute | Seal-In Circuit | Latch Logic | |---|---|---| | Typical instruction pattern | OTE with parallel holding branch | OTL/OTU or SET/RESET | | State source | Current rung continuity | Retained bit state | | Scan-cycle behavior | Must remain true through valid rung path | Can stay true after initiating condition disappears | | Power-loss behavior | Typically drops out on power loss or restart | May remain set if retentive and not explicitly reset | | Reset method | Rung false condition, stop condition, permissive loss | Explicit unlatch or reset instruction | | Best-fit use case | Motor run commands, self-holding command paths, restart-sensitive outputs | Alarm capture, state memory, explicit sequencers, acknowledged events | | Main risk | Incomplete permissive design | Trapped state and unexpected restart if reset strategy is weak |
What does IEC 61131-3 help clarify here?
IEC 61131-3 standardizes PLC programming languages and instruction concepts, but it does not remove the need to define memory behavior clearly. The practical engineering distinction remains whether the implementation is retentive or non-retentive and how that behavior is handled during startup, shutdown, and fault recovery.
In other words, syntax is not the hard part. Startup behavior is.
How does NFPA 79 affect the choice between seal-in and latch logic?
NFPA 79 makes restart behavior a safety issue, not a stylistic preference.
The relevant design principle is straightforward: machinery must not automatically restart on restoration of power if that restart can create a hazardous condition. ISO 13849-1 aligns with the same broader safety logic through prevention of hazardous machine behavior and proper treatment of reset, interlock, and control-system response.
This is why a traditional 3-wire motor control pattern remains so durable. A start pushbutton energizes the command, a stop device breaks it, and loss of power drops the run command out. When power returns, the machine stays stopped until an intentional restart command is given.
Why does a seal-in rung align naturally with restart prevention?
A seal-in rung usually mirrors the operating logic of a 3-wire control circuit:
- A Start condition momentarily becomes true
- A parallel holding contact keeps the rung true after Start is released
- A Stop, fault, or permissive loss breaks the rung
- Loss of controller power removes the active output state
- On restart, the output remains off until commanded again
That behavior is not automatically safe in every context, but it is generally easier to reason about and easier to validate for restart prevention.
Why does latch logic require more deliberate safety design?
A latch can bypass the natural dropout behavior of the command path.
If a run bit is latched and no startup-clear logic exists, the controller may return from a power cycle with that bit still true. If downstream permissives are also satisfied, motion may resume without a fresh operator command. That is exactly the kind of behavior restart-prevention rules are meant to stop.
Where latch logic is used in restart-sensitive functions, engineers commonly need:
- A first-scan reset or startup-clear routine
- Explicit separation of command memory from output energization
- Revalidation of all permissives before any output can re-energize
- Reset behavior consistent with the machine risk assessment
A latch is not wrong. An unexamined latch is.
Why do latch instructions create trapped states during scan interruptions?
Latch instructions create trapped states because they do not require the original enabling condition to remain true.
Once the latch bit is set, it stays set until an unlatch executes. If the sequence that should clear it never completes, the bit remains high. This can happen during:
- Power loss before the OTU or reset rung is scanned
- Mode changes from Auto to Manual mid-sequence
- E-stop recovery with incomplete state clearing
- Fault aborts that skip the normal sequence-exit path
- Partial downloads or test edits during commissioning
- Operator navigation that resets one part of the sequence but not the retained state
This is one reason junior code often works in a happy-path demo and fails during abnormal recovery.
What is a trapped state in practical terms?
A trapped state is a retained command or sequence bit that remains true after the process context that justified it has disappeared.
Examples include:
- A conveyor run request that survives a simulated power cycle
- A pump lead command that remains set after HOA mode changes
- A sequence step bit that stays active after a fault abort
- A faulted actuator command that reappears after reboot because the reset path was conditional and never scanned
The engineering problem is not that the bit is retained. The problem is that the retained state is no longer valid for the current plant condition.
When are latch instructions appropriate?
Latch instructions are appropriate when retained memory is intentional, bounded, and reset deliberately.
Safe and common use cases include:
- Alarm capture: Holding a transient fault until operator acknowledgment - Recipe or batch state retention: Preserving controlled process context through planned pauses - Explicit state machines: Managing step-state memory where startup and abort handling are fully defined - Maintenance events: Recording service-required conditions until reviewed and reset
The pattern is simple: use latches for remembering, not for pretending a command path still exists.
How should a PLC engineer decide between OTE and OTL/OTU?
Choose OTE-based seal-in logic for outputs that must drop out when command continuity, permissives, or power are lost.
Choose OTL/OTU-style latch logic only when retained state is operationally necessary and when startup-clear, abort-clear, and fault-recovery behavior are explicitly designed and tested.
A practical decision rule is:
- If the bit represents present authority to run, prefer a non-retentive pattern
- If the bit represents remembered history or acknowledged state, a retentive pattern may be justified
- If hazardous motion could resume after reboot, treat retentive logic as suspect until proven safe
A compact engineering test
Ask one question: If power disappears at the worst possible moment, what exact bit state do I want when the controller comes back?
If the answer is “off until re-commanded,” a seal-in pattern is usually the cleaner starting point.
If the answer is “remember this state, but do not energize anything until startup logic validates conditions,” then a latch may be acceptable, provided the separation is implemented correctly.
What does “Simulation-Ready” mean for seal-in vs. latch validation?
Simulation-Ready means the engineer can prove, observe, diagnose, and harden restart behavior before logic reaches a live process.
For this article, the term is defined operationally. An engineer is Simulation-Ready when they can:
- Trace the causal path from input to output in the ladder logic
- Induce a simulated power-loss event
- Observe which bits, outputs, and process states drop out or persist
- Verify that hazardous motion or process action does not resume unintentionally on restart
- Revise the logic and retest until restart behavior is deterministic and documented
That is materially different from “I can write ladder syntax.”
Observable behaviors that satisfy the definition
A restart-validation exercise is Simulation-Ready only if the engineer can show:
- Which tags are non-retentive and which are retentive
- What the machine or process model does during loss of power
- What happens on restart before any operator action
- Whether the PV, actuator state, or motion command returns to a hazardous condition
- What logic revision was made to prevent that outcome
The standard here is evidence, not confidence.
How can you simulate power-cycle behavior in OLLA Lab?
Power-cycle behavior should be tested in simulation before anyone is tempted to try it on the machine.
OLLA Lab is useful here as a bounded validation environment. It allows the engineer to build ladder logic, run it in simulation, inspect variables and I/O state, and compare ladder-state behavior against a simulated machine or process context.
A practical OLLA Lab workflow for restart validation
Use this sequence:
- Version A: standard seal-in rung using a non-retentive output pattern - Version B: retentive latch or unlatch pattern for the same command
- Start command
- Stop command
- Run permissive
- Motor run output
- Latched run request bit
- Fault bit
- Any relevant analog PV or feedback
- Start the machine or simulated unit
- Confirm expected output energization
- Confirm feedback and status tags
- Toggle the relevant main power or controller state in the simulation workflow
- Stop the logic execution if required by the scenario
- Observe which bits clear and which remain set
- Do not issue a fresh start command
- Observe output state, sequence state, and process state immediately after restart
- Did the output remain de-energized?
- Did any retained bit reassert a command?
- Did the simulated equipment resume motion or process action?
- Add first-scan unlatch logic or startup-clear handling where needed
- Re-run the same power-cycle test
- Verify deterministic safe-state recovery
- Build two versions of the command logic
- Define the monitored tags
- Run the normal sequence
- Inject a simulated power-loss event
- Restore power and restart execution
- Record the result
- Revise and retest
What should you watch in the Variables Panel?
The Variables Panel should be used to observe both logical state and process consequence.
Watch for:
- Command bits that remain true after restart
- Outputs that energize without a new start command
- Permissives that revalidate too early
- Sequence steps that resume mid-state
- Analog values or feedbacks that imply resumed process activity
- PID-related outputs that return to prior demand without controlled restart handling
A bit staying high is not automatically dangerous. A bit staying high and re-energizing a physical action path is where the risk increases.
What should a safe seal-in rung and a risky latch pattern look like?
The safest comparison is conceptual, because exact instruction names vary by PLC family. The distinction still holds.
### Example: seal-in motor command pattern
A typical seal-in pattern uses a stop condition, fault condition, start condition, and a parallel holding branch around the start input to maintain a non-retentive motor run command while valid conditions remain true.
Behavior:
- Start momentarily energizes `Motor_Run`
- `Motor_Run` contact seals the rung in
- Stop, fault, or permissive loss breaks the rung
- On power loss or restart, `Motor_Run` does not remain asserted by memory alone
### Example: retentive latch pattern
A typical retentive pattern uses a start condition to set a retained run bit, separate stop or fault conditions to clear it, and a downstream rung that drives the motor output from the retained bit.
Risk:
- `Run_Latch` may remain set if the unlatch path is not executed before interruption
- On restart, `Motor_Run` may re-energize if `Run_Latch` is still true and permissives pass
What does a safer startup-clear strategy look like?
If retentive logic is justified, startup handling must be explicit.
A common pattern is to use a first-scan condition to clear retained run and sequence bits during startup. The exact implementation depends on platform and risk assessment, but the principle is stable: clear retained command states on startup unless retention is intentionally required and separately governed.
How do you prove that power-loss recovery is correct?
You prove power-loss recovery by documenting behavior against a defined standard of correctness, not by saying the simulation looked fine.
Use this engineering evidence structure:
State the exact expected behavior after power restoration. Example: “No motor output shall energize until a new Start command is issued after restart.”
Specify the interruption: controller power loss, sequence abort, mode change, fault trip, or communications drop.
Show the logic correction: startup-clear routine, permissive restructuring, state-machine reset, or output gating.
- System Description Identify the machine or process function, major I/O, operating mode, and restart hazard.
- Operational definition of correct
- Ladder logic and simulated equipment state Capture the relevant rung logic, tag states, and simulated equipment condition before and after the event.
- The injected fault case
- The revision made
- Lessons learned Record what failed, why it failed, and how the revised logic changed restart behavior.
What are the most common mistakes engineers make with latch logic?
The most common mistake is using a latch to solve a sequencing inconvenience without designing the reset path with equal care.
Other recurring errors include:
- Latching a run command instead of a state memory bit
- Assuming the unlatch rung will always execute
- Clearing retained bits only in one operating mode
- Forgetting startup-clear behavior after power restoration
- Mixing operator reset, fault reset, and startup reset into one ambiguous path
- Allowing a retained state to drive an output directly
- Testing only normal shutdown instead of abnormal interruption
These mistakes are common because latch logic feels efficient. It often is efficient, but it can also hide restart risk if not reviewed carefully.
When should OLLA Lab be used in this workflow?
OLLA Lab should be used before live commissioning whenever restart behavior, sequence persistence, fault recovery, or I/O causality needs to be rehearsed without plant risk.
That positioning should stay bounded. OLLA Lab is not a substitute for formal site acceptance, machine risk assessment, functional safety validation, or plant-specific startup procedures. It is a controlled environment for practicing and validating logic behaviors that are too risky, too disruptive, or too expensive to learn first on live equipment.
In this use case, OLLA Lab is operationally useful because it lets the engineer:
- Build and compare seal-in and latch patterns
- Observe tag-level state retention
- Inject restart and fault scenarios
- Compare ladder state against simulated equipment behavior
- Revise logic before field exposure
Conclusion
Choose seal-in logic when the command should exist only while present conditions justify it. Choose latch logic only when retained state is necessary and reset behavior is explicitly engineered.
The safety issue is not whether the rung works. The safety issue is what survives interruption, what restarts on reboot, and whether that behavior is acceptable for the machine. NFPA 79 and sound control practice both point in the same direction: hazardous restart should be prevented by design.
A useful final contrast is this: seal-in logic expresses continuity; latch logic expresses memory. Confusing those two is how trapped states become commissioning problems.
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